1. Field of the Invention
The present invention relates to a direct memory access controller performing a data transfer by using a direct memory access.
2. Description of the Related Art
FIG. 2 is a view showing a configuration example of a direct memory access controller (DMAC) 101 and an external memory 102. The DMAC 101 has a control setting register 211, a transfer destination address setting register 212, a transfer source address setting register 213, a resource enable register 214, an interrupt factor register 215, a descriptor start address setting register 216, a status register 217, and a counter 221. The external memory 102 stores a descriptor 204. The descriptor 204 includes a control setting register 201, a transfer destination address setting register 202, and a transfer source address setting register 203 by each channel number.
Transfer request signals REQ are inputted to the DMAC 101 from plural resources respectively having channel numbers, and the DMAC 101 loads control setting information, a transfer destination address, and a transfer source address from the control setting register 201, the transfer destination address setting register 202, and the transfer source address setting register 203 inside of the external memory 102 corresponding to the channel number, to the control setting register 211, the transfer destination address setting register 212, and the transfer source address setting register 213 inside of the DMAC 101. The external memory 102 stores the control setting information, the transfer destination address, and the transfer source address by each channel number, and the DMAC 101 performs the load of the above from the external memory 102 to the DMAC 101 every time when the channel number of the transfer request signal REQ changes.
A descriptor control system is described in Patent Document 1 stated below, in which a DMAC is connected to an external storage area via a bus, the external storage area includes a descriptor, and the DMAC is controlled by using the descriptor.
Besides, a data transfer device is described in Patent Document 2 stated below, in which a direct memory access transfer is performed in accordance with plural descriptors continuously set in an external storage area beforehand.
[Patent Document 1] Japanese Patent Application Laid-open No. Hei 4-277850
[Patent Document 2] Japanese Patent Application Laid-open No. Hei 4-177445
In the DMAC 101 of the descriptor control system, there is a problem in which a setting of the descriptor 204 must be loaded from the external memory 102 when the transfer request signal REQ of another channel number is generated even if a setting value is the same.